1. Field of the Invention
The present invention relates to a display device, and more particularly to a display device with a built-in driving circuit.
2. Description of the Related Art
Since a TFT (thin-film transistor) type liquid crystal display module using a thin-film transistor as an active element is capable of displaying high-resolution images, it is used as a display device for television sets, personal computers, or the like.
As the TFT type liquid crystal display module, a liquid crystal display module with a built-in driving circuit without the need for an external driver (LSI) is known (refer to JP-A-2003-344824).
With a liquid crystal display module with a built-in driving circuit, a driving circuit (for example, a drain driver or a gate driver) is integrally formed with and at the periphery of a display area on one substrate on which a pixel transistor (TFT) for each sub pixel in the display area is formed.
With the liquid crystal display module with a built-in driving circuit, amorphous silicon or poly-silicon is used as a semiconductor layer for a thin-film transistor (TFT) in the built-in driving circuit. A thin-film transistor having a semiconductor layer of poly-silicon has higher mobility than a thin-film transistor having a semiconductor layer of amorphous silicon.
FIG. 4 is a block diagram showing an example of a built-in driving circuit in a conventional liquid crystal display device with a built-in driving circuit.
With the driving circuit shown in FIG. 4, display data (D0) serially inputted as digital data is first changed to a high-voltage amplitude by a level shift circuit (LS), passes through a transmission line (LIN) and an inverter series (LINV) for improving the internal drive performance, and then is inputted to a latch circuit (LACH).
On the other hand, a display data synchronization clock (DCK) and a horizontal synchronization signal (Hsync) are also changed to a high-voltage amplitude by the level shift circuit (LS) and then inputted to a driving pulse generation circuit (POC). The driving pulse generation circuit (POC) outputs a driving pulse for driving a shift register based on the display data synchronization clock (DCK) and the horizontal synchronization signal (Hsync).
The shift register (SR) sequentially supplies a scanning signal (SR-OUT) to a plurality of latch circuits (LACH).
Each latch circuit (LACH) captures (or latches) the display data (D0) serially inputted based on the scanning signal (SR-OUT) and then supplies the data to an internal processing circuit (a D/A converter circuit or a pixel array) (ICIR).
Also for the scanning signal (SR-OUT) generated from the display data synchronization clock (DCK) and the horizontal synchronization signal (Hsync), inverters are inserted at necessary positions in order to improve the internal drive performance. However, these inverters are omitted in FIG. 4.
A conventional technique related to the present specification is disclosed in JP-A-2003-344824.